As semiconductor process technologies have continued to shrink in size, gate dielectrics used to form transistors and other active devices have suffered from increased leakage. Accordingly, new high dielectric constant (high-K) dielectrics were introduced that required polysilicon (poly) gates to be replaced with independently optimized thin work-function metals. Formation of these metal gates typically occurred after the source and drain regions were formed because of the high annealing temperatures used in the source and drain regions. The metal gate formation is called High-K Metal Gate (HKMG) or sometimes Replacement Metal Gate (RMG) because the poly used to mask or define the source and drain regions is exposed with a Chemical Mechanical Polish (CMP) and subsequently replaced with metal. The CMP exposes the sacrificial poly gate by a process called Poly Open Planarization (POP).
In an advanced embedded memory process, the logic devices use the HKMG process where the poly gate is replaced with metal, however the devices in the memory still require a poly gate due in part to the different gate oxide used by the memory devices.